1. Field of the Invention
The present invention relates to semiconductor devices. In particular, the present invention relates to a differential current sense amplifier for semiconductor memory caches.
2. Background of the Related Art
Semiconductor memory devices are used in a wide variety of products and applications to store data. Conventional semiconductor memory devices use voltage sense amplifiers to sense or detect stored data from a selected memory cell. FIG. 1 shows a typical use of a voltage sense amplifier in a memory device. The memory cell being read produces a current (ID) that removes some of the charge (dQ) stored on the pre-charged bit-lines. Since the bit-lines are long and shared by other memory cells, the parasitic resistance (RBL) and capacitance (CBL) are very large. Therefore, the resulting bit-line voltage swing (dVBL) caused by the removal of the charge (dQ) from the bit-line is very small (dVBL=dQ/CBL). Voltage sense amplifiers amplify this small voltage to a more useful full logic signal that can be used by the logic circuit that requires signals to be above a threshold voltage.
One example of a voltage sense amplifier is shown in FIG. 2. The voltage sense amplifier includes a bistable element embodied by a pair of cross-coupled P-channel devices and a pair of cross-coupled N-channel devices. The sources of the P-channel devices are connected to a positive power supply with respect to ground. The sources of the N-channel devices are tied to a positive power supply through another P-channel device and a ground through another N-channel device, and driven by sense amplifier enable line (SAen). The output nodes of the bistable element are coupled to differential bit lines (bl and bl#) through a pair of P-channel pass gates (controlled by Ysel) and drive output lines (SAout and SAout#) through respective inverters. However, the need for higher speed, increased memory capacity, and lower power consumption has presented numerous problems for memory devices that use voltage sense amplifiers.
The time for the voltage swing/differential voltage to appear depends on the bit-line capacitance (CBL). Hence, the time to develop a certain differential voltage will increase with the increase in capacitance (i.e. number of memory cells in the column). The energy consumption depends on the bit-line resistance (RBL). Thus, power requirements of the memory device will increase with the increase in resistance (length of the bit lines). Decreasing memory cell area to integrate more memory on a single chip reduces the current (ID) that is driving the now heavily loaded bit-line. This, in combination with increased capacitance, causes even smaller voltage swings on the bit-line. Lower power consumption requirements have resulted in decreased supply voltages resulting in smaller noise margins. Accordingly, there is a need for sense amplifiers with higher reliability.